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Modern Hardware Description Languages (HDLs) such as SystemVerilog or VHDLare, due to their sheer complexity, insufficient to transport designs throughmodern circuit design flows. Instead, each design automation tool lowers HDLsto its own Intermediate Representation (IR). These tools are monolithic andmostly proprietary, disagree in their implementation of HDLs, and while manyredundant IRs exists, no IR today can be used through the entire circuit designflow. To solve this problem, we propose the LLHD multi-level IR. LLHD isdesigned as simple, unambiguous reference description of a digital circuit, yetfully captures existing HDLs. We show this with our reference compiler ondesigns as complex as full CPU cores. LLHD comes with lowering passes to ahardware-near structural IR, which readily integrates with existing tools. LLHDestablishes the basis for innovation in HDLs and tools without redundantcompilers or disjoint IRs. For instance, we implement an LLHD simulator thatruns up to 2.4x faster than commercial simulators but produces equivalent,cycle-accurate results. An initial vertically-integrated research prototype iscapable of representing all levels of the IR, implements lowering from thebehavioural to the structural IR, and covers a sufficient subset ofSystemVerilog to support a full CPU design.

LLHD: A Multi-level Intermediate Representation for Hardware Description Languages