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After a plethora of high-profile RowHammer attacks, CPU and DRAM vendorsscrambled to deliver what was meant to be the definitive hardware solutionagainst the RowHammer problem: Target Row Refresh (TRR). A common belief amongpractitioners is that, for the latest generation of DDR4 systems that areprotected by TRR, RowHammer is no longer an issue in practice. However, inreality, very little is known about TRR. In this paper, we demystify the innerworkings of TRR and debunk its security guarantees. We show that what isadvertised as a single mitigation mechanism is actually a series of differentsolutions coalesced under the umbrella term TRR. We inspect and disclose, via adeep analysis, different existing TRR solutions and demonstrate that modernimplementations operate entirely inside DRAM chips. Despite the difficulties ofanalyzing in-DRAM mitigations, we describe novel techniques for gaininginsights into the operation of these mitigation mechanisms. These insightsallow us to build TRRespass, a scalable black-box RowHammer fuzzer. TRRespassshows that even the latest generation DDR4 chips with in-DRAM TRR, immune toall known RowHammer attacks, are often still vulnerable to new TRR-awarevariants of RowHammer that we develop. In particular, TRRespass finds that, onmodern DDR4 modules, RowHammer is still possible when many aggressor rows areused (as many as 19 in some cases), with a method we generally refer to asMany-sided RowHammer. Overall, our analysis shows that 13 out of the 42 modulesfrom all three major DRAM vendors are vulnerable to our TRR-aware RowHammeraccess patterns, and thus one can still mount existing state-of-the-artRowHammer attacks. In addition to DDR4, we also experiment with LPDDR4 chipsand show that they are susceptible to RowHammer bit flips too. Our resultsprovide concrete evidence that the pursuit of better RowHammer mitigations mustcontinue.

TRRespass: Exploiting the Many Sides of Target Row Refresh