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A common theme of data acquisition systems is the transport of data fromdigitising front-end modules to stable storage and online analysis. A goodchoice today is to base this on the ubiquitous, commercially and cheaplyavailable Ethernet technology. A firmware building block to turn already theFPGA of front-end electronics into a TCP data source and UDP control interfaceusing a data-flow architecture is presented. The overall performance targetsare to be able to saturate a 1 Gbps network link with outbound data, whileusing few FPGA resources. The goal is to replace the use of custom data busesand protocols with ordinary Ethernet equipment. These objectives are achievedby being just-enough conforming, such that no special drivers are needed in thePC equipment interfacing with the here presented Fakernet system. An importantdesign choice is to handle all packet-data internally as 16-bit words, thusreducing the clock-speed requirements. An advantageous circumstance is thateven at 1 Gbps speeds, for local network segments, the round-trip times areusually well below 500 microseconds. Thus, less than 50 kiB of unacknowledgeddata needs to be in-flight, allowing to saturate a network link without TCPwindow scaling. The Fakernet system has so far been shown to saturate a 100Mbps link at 11.7 MB/s of TCP output data, and able to do 32-bit controlregister accesses at over 450 kword/s.

Fakernet -- small and fast FPGA-based TCP and UDP communication