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Network-on-Chip (NoC) paradigm has been proposed as an auspicious solution tohandle the strict communication requirements between the increasingly largenumber of cores on a single multi and many-core chips. However, NoC systems areexposed to a variety of manufacturing, design and energetic particles factorsmaking them vulnerable to permanent (hard) faults and transient (soft) errors.In this paper, we present a comprehensive soft error and hard fault tolerant3D-NoC architecture, named 3D-Hard-Fault-Soft-Error-Tolerant-OASIS-NoC(3D-FETO). With the aid of adaptive algorithms, 3D-FETO is capable of detectingand recovering from soft errors occurring in the routing pipeline stages and isleveraging on reconfigurable components to handle permanent faults occurrencein links, input buffers, and crossbar. In-depth evaluation results show thatthe 3D-FETO system is able to work around different kinds of hard faults andsoft errors while ensuring graceful performance degradation, minimizing theadditional hardware complexity and remaining power-efficient.

Soft-Error and Hard-fault Tolerant Architecture and Routing Algorithm for Reliable 3D-NoC Systems