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In this paper a low power multiplier is proposed. The proposed multiplierutilizes Broken-Array Multiplier approximation method on the conventionalmodified Booth multiplier. This method reduces the total power consumption ofmultiplier up to 58% at the cost of a small decrease in output accuracy. Theproposed multiplier is compared with other approximate multipliers in terms ofpower consumption and accuracy. Furthermore, to have a better evaluation of theproposed multiplier efficiency, it has been used in designing a 30-tap low-passFIR filter and the power consumption and accuracy are compared with that of afilter with conventional booth multipliers. The simulation results show a 17.1%power reduction at the cost of only 0.4dB decrease in the output SNR.

New Approximate Multiplier for Low Power Digital Signal Processing