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DNN+NeuroSim is an integrated framework to benchmark compute-in-memory (CIM)accelerators for deep neural networks, with hierarchical design options fromdevice-level, to circuit-level and up to algorithm-level. A python wrapper isdeveloped to interface NeuroSim with a popular machine learning platform:Pytorch, to support flexible network structures. The framework providesautomatic algorithm-to-hardware mapping, and evaluates chip-level area, energyefficiency and throughput for training or inference, as well astraining/inference accuracy with hardware constraints. Our prior work(DNN+NeuroSim V1.1) was developed to estimate the impact of reliability insynaptic devices, and analog-to-digital converter (ADC) quantization loss onthe accuracy and hardware performance of inference engines. In this work, wefurther investigated the impact of the analog emerging non-volatile memorynon-ideal device properties for on-chip training. By introducing thenonlinearity, asymmetry, device-to-device and cycle-to-cycle variation ofweight update into the python wrapper, and peripheral circuits for error/weightgradient computation in NeuroSim core, we benchmarked CIM accelerators based onstate-of-the-art SRAM and eNVM devices for VGG-8 on CIFAR-10 dataset, revealingthe crucial specs of synaptic devices for on-chip training. The proposedDNN+NeuroSim V2.0 framework is available on GitHub.

DNN+NeuroSim V2.0: An End-to-End Benchmarking Framework for Compute-in-Memory Accelerators for On-chip Training