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Recent advances demonstrate that irregularly wired neural networks fromNeural Architecture Search (NAS) and Random Wiring can not only automate thedesign of deep neural networks but also emit models that outperform previousmanual designs. These designs are especially effective while designing neuralarchitectures under hard resource constraints (memory, MACs, . . . ) whichhighlights the importance of this class of designing neural networks. However,such a move creates complication in the previously streamlined pattern ofexecution. In fact one of the main challenges is that the order of such nodesin the neural network significantly effects the memory footprint of theintermediate activations. Current compilers do not schedule with regard toactivation memory footprint that it significantly increases its peak comparedto the optimum, rendering it not applicable for edge devices. To address thisstanding issue, we present a memory-aware compiler, dubbed SERENITY, thatutilizes dynamic programming to find a sequence that finds a schedule withoptimal memory footprint. Our solution also comprises of graph rewritingtechnique that allows further reduction beyond the optimum. As such, SERENITYachieves optimal peak memory, and the graph rewriting technique furtherimproves this resulting in 1.68x improvement with dynamic programming-basedscheduler and 1.86x with graph rewriting, against TensorFlow Lite with lessthan one minute overhead.

Ordering Chaos: Memory-Aware Scheduling of Irregularly Wired Neural Networks for Edge Devices