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The recent breakthroughs in deep neural networks (DNNs) have spurred atremendously increased demand for DNN accelerators. However, designing DNNaccelerators is non-trivial as it often takes months/years and requirescross-disciplinary knowledge. To enable fast and effective DNN acceleratordevelopment, we propose DNN-Chip Predictor, an analytical performance predictorwhich can accurately predict DNN accelerators' energy, throughput, and latencyprior to their actual implementation. Our Predictor features two highlights:(1) its analytical performance formulation of DNN ASIC/FPGA acceleratorsfacilitates fast design space exploration and optimization; and (2) it supportsDNN accelerators with different algorithm-to-hardware mapping methods (i.e.,dataflows) and hardware architectures. Experiment results based on 2 DNN modelsand 3 different ASIC/FPGA implementations show that our DNN-Chip Predictor'spredicted performance differs from those of chip measurements of FPGA/ASICimplementation by no more than 17.66% when using different DNN models, hardwarearchitectures, and dataflows. We will release code upon acceptance.

DNN-Chip Predictor: An Analytical Performance Predictor for DNN Accelerators with Various Dataflows and Hardware Architectures