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Convolutional Neural Networks (CNNs) have shown outstanding accuracy for manyvision tasks during recent years. When deploying CNNs on portable devices andembedded systems, however, the large number of parameters and computationsresult in long processing time and low battery life. An important factor indesigning CNN hardware accelerators is to efficiently map the convolutioncomputation onto hardware resources. In addition, to save battery life andreduce energy consumption, it is essential to reduce the number of DRAMaccesses since DRAM consumes orders of magnitude more energy compared to otheroperations in hardware. In this paper, we propose an energy-efficientarchitecture which maximally utilizes its computational units for convolutionoperations while requiring a low number of DRAM accesses. The implementationresults show that the proposed architecture performs one image recognition taskusing the VGGNet model with a latency of 393 ms and only 251.5 MB of DRAMaccesses.

An Energy-Efficient Accelerator Architecture with Serial Accumulation Dataflow for Deep CNNs