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In neural network topologies, algorithms are running on batches of datatensors. The batches of data are typically scheduled onto the computing coreswhich execute in parallel. For the algorithms running on batches of data, anoptimal batch scheduling architecture is very much needed by suitably utilizinghardware resources - thereby resulting in significant reduction training andinference time. In this paper, we propose to accelerate the batch algorithmsfor neural networks through a scheduling architecture enabling optimal computepower utilization. The proposed optimal scheduling architecture can be builtinto HW or can be implemented in SW alone which can be leveraged foraccelerating batch algorithms. The results demonstrate that the proposedarchitecture speeds up the batch algorithms compared to the previous solutions.The proposed idea applies to any HPC architecture meant for neural networks.

An optimal scheduling architecture for accelerating batch algorithms on Neural Network processor architectures