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Evolutionary algorithms can outperform conventional placement algorithms suchas simulated annealing, analytical placement as well as manual placement onmetrics such as runtime, wirelength, pipelining cost, and clock frequency whenmapping FPGA hard block intensive designs such as systolic arrays on XilinxUltraScale+ FPGAs. For certain hard-block intensive, systolic array acceleratordesigns, the commercial-grade Xilinx Vivado CAD tool is unable to provide alegal routing solution without tedious manual placement constraints. Instead,we formulate an automatic FPGA placement algorithm for these hard blocks as amulti-objective optimization problem that targets wirelength squared andmaximum bounding box size metrics. We build an end-to-end placement and routingflow called RapidLayout using the Xilinx RapidWright framework. RapidLayoutruns 5-6$\times$ faster than Vivado with manual constraints and eliminates theweeks-long effort to generate placement constraints manually for the hardblocks. We also perform automated post-placement pipelining of the long wiresinside each convolution block to target 650MHz URAM-limited operation.RapidLayout outperforms (1) the simulated annealer in VPR by 33% in runtime,1.9-2.4$\times$ in wirelength, and 3-4$\times$ in bounding box size, while also(2) beating the analytical placer UTPlaceF by 9.3$\times$ in runtime,1.8-2.2$\times$ in wirelength, and 2-2.7$\times$ in bounding box size. Weemploy transfer learning from a base FPGA device to speed-up placementoptimization for similar FPGA devices in the UltraScale+ family by11-14$\times$ than learning the placements from scratch.

RapidLayout: Fast Hard Block Placement of FPGA-optimized Systolic Arrays using Evolutionary Algorithms