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Neural Architecture Search (NAS) has demonstrated its power on various AIaccelerating platforms such as Field Programmable Gate Arrays (FPGAs) andGraphic Processing Units (GPUs). However, it remains an open problem, how tointegrate NAS with Application-Specific Integrated Circuits (ASICs), despitethem being the most powerful AI accelerating platforms. The major bottleneckcomes from the large design freedom associated with ASIC designs. Moreover,with the consideration that multiple DNNs will run in parallel for differentworkloads with diverse layer operations and sizes, integrating heterogeneousASIC sub-accelerators for distinct DNNs in one design can significantly boostperformance, and at the same time further complicate the design space. Toaddress these challenges, in this paper we build ASIC template set based onexisting successful designs, described by their unique dataflows, so that thedesign space is significantly reduced. Based on the templates, we furtherpropose a framework, namely NASAIC, which can simultaneously identify multipleDNN architectures and the associated heterogeneous ASIC accelerator design,such that the design specifications (specs) can be satisfied, while theaccuracy can be maximized. Experimental results show that compared withsuccessive NAS and ASIC design optimizations which lead to design specviolations, NASAIC can guarantee the results to meet the design specs with17.77%, 2.49x, and 2.32x reductions on latency, energy, and area and with 0.76%accuracy loss. To the best of the authors' knowledge, this is the first work onneural architecture and ASIC accelerator design co-exploration.

Co-Exploration of Neural Architectures and Heterogeneous ASIC Accelerator Designs Targeting Multiple Tasks