English (United Kingdom)

https://curated-unify.zendy.io/wp-json/zendy-region/v1/featured_content/oa?rat=en

https://curated-unify.zendy.io/wp-json/zendy-region/v1/highlighted_journal/

Global: Zendy Plus annual

Presents the access of premium content as premium feature

Premium Content

Presents the keyphrase highlighting as premium feature

Keyphrase Highlighting

Presents the summarisation as premium feature

Summarisation

Insights

Presents the pdf analysis as premium feature

PDF Analysis

Presents the zaia usage as premium feature

ZAIA

Global: Zendy Plus monthly

Global: Zendy Tools annual

Global: Zendy Tools monthly

Global: Zendy Free Plan

Single flux quantum (SFQ) circuits are an attractive beyond-CMOS technologybecause they promise two orders of magnitude lower power at clock frequenciesexceeding 25 GHz.However, every SFQ gate is clocked creating very deepgate-level pipelines that are difficult to keep full, particularly forsequences that include data-dependent operations. This paper proposes toincrease the throughput of SFQ pipelines by re-designing the datapath to acceptand operate on least-significant bits (LSBs) clock cycles earlier than moresignificant bits. This skewed datapath approach reduces the latency of the LSBside which can be feedback earlier for use in subsequent data-dependentoperations increasing their throughput. In particular,we propose to group thebits into 4-bit blocks that are operatedon concurrently and create block-skeweddatapath units for 32-bit operation. This skewed approach allows a subsequentdata-dependent operation to start evaluating as soon as the first 4-bit blockcompletes. Using this general approach, we developa block-skewedMIPS-compatible 32-bit ALU. Our gate-level Verilog design improves thethroughput of 32-bit data dependent operations by 2x and 1.5x compared topreviously proposed 4-bit bit-slice and 32-bit Ladner-Fischer ALUsrespectively.

qBSA: Logic Design of a 32-bit Block-Skewed RSFQ Arithmetic Logic Unit