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This paper shows how the input offset of sampling flip-flops in the Alexanderphase detector affects the jitter transfer from data to the recovered clock ina clock data recovery circuit. The Alexander phase detector samples the data atboth the edges of the clock in order to recover the data, as well as the clocktiming information. The timing information is used in a clock recovery circuit,which is basically a PLL or a DLL. Once the PLL (or DLL) is locked, the phasedetector samples the data at the center of the eye as well as at the datatransitions. It is shown how the offset of the sampling flip-flop that samplesthe data at its transitions influences the jitter transfer from data to therecovered clock. Importantly, it is shown that zero offset is not always thebest case. The effect is studied for different levels of data dependent jitter.The mechanism of this phenomenon is explained and the predictions are supportedwith simulations. The paper also discusses a tracking circuit that keeps theoffset at the minimum jitter point.

Impact of Sampler Offset on Jitter Transfer in Clock and Data Recovery Circuits