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Intellectual Property (IP) infringement including piracy and over productionhave emerged as significant threats in the semiconductor supply chain. Keybased obfuscation techniques (i.e., logic locking) are widely applied to securelegacy IP from such attacks. However, the fundamental question remains openwhether an attacker is allowed an exponential amount of time to seek correctkey or could it be useful to lock out the design in a non-destructive mannerafter several incorrect attempts. In this paper, we address this question witha robust design lockout technique. Specifically, we perform comparisons onobfuscation logic output that reflects the condition (correct or incorrect) ofthe applied key without changing the system behaviour. The proposed approach,when combined with key obfuscation (logic locking) technique, increases thedifficulty of reverse engineering key obfuscated RTL module. We providesecurity evaluation of DLockout against three common side channel attacksfollowed by a quantitative assessment of the resilience. We conducted a set ofexperiments on four datapath intensive IPs and one crypto core for threedifferent key lengths (32-, 64-, and 128-bit) under typical design corner. Onaverage, DLockout incurs negligible area, power, and delay overheads.

DLockout: A Design Lockout Technique for Key Obfuscated RTL IP Designs