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The computing wall and data movement challenges of deep neural networks(DNNs) have exposed the limitations of conventional CMOS-based DNNaccelerators. Furthermore, the deep structure and large model size will makeDNNs prohibitive to embedded systems and IoT devices, where low powerconsumption are required. To address these challenges, spin orbit torquemagnetic random-access memory (SOT-MRAM) and SOT-MRAM basedProcessing-In-Memory (PIM) engines have been used to reduce the powerconsumption of DNNs since SOT-MRAM has the characteristic of near-zero standbypower, high density, none-volatile. However, the drawbacks of SOT-MRAM basedPIM engines such as high writing latency and requiring low bit-width datadecrease its popularity as a favorable energy efficient DNN accelerator. Tomitigate these drawbacks, we propose an ultra energy efficient framework byusing model compression techniques including weight pruning and quantizationfrom the software level considering the architecture of SOT-MRAM PIM. And weincorporate the alternating direction method of multipliers (ADMM) into thetraining phase to further guarantee the solution feasibility and satisfySOT-MRAM hardware constraints. Thus, the footprint and power consumption ofSOT-MRAM PIM can be reduced, while increasing the overall system throughput atthe meantime, making our proposed ADMM-based SOT-MRAM PIM more energyefficiency and suitable for embedded systems or IoT devices. Our experimentalresults show the accuracy and compression rate of our proposed framework isconsistently outperforming the reference works, while the efficiency (area \&power) and throughput of SOT-MRAM PIM engine is significantly improved.

A SOT-MRAM-based Processing-In-Memory Engine for Highly Compressed DNN Implementation