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To improve power efficiency, researchers are experimenting with dynamicallyadjusting the supply voltage of systems below the nominal operating points.However, production systems are typically not allowed to function on voltagesettings that is below the reliable limit. Consequently, existing softwarefault tolerance studies are based on fault models, which inject faults onrandom fault locations using fault injection techniques. In this work we studywhether random fault injection is accurate to simulate the behavior ofundervolted SRAMs.  Our study extends the Gem5 simulator to support fault injection on the cachesof the simulated system. The fault injection framework uses fault maps, whichdescribe the faulty bits of SRAMs, as inputs. To compare random fault injectionand hardware guided fault injection, we use two types of fault maps. The firsttype of maps are created through undervolting real SRAMs and observing thelocation of the erroneous bits, whereas the second type of maps are created bycorrupting random bits of the SRAMs. During our study we corrupt the L1-Dcacheof the simulated system and we monitor the behavior of the two types of faultmaps on the resiliency of six benchmarks. The difference among the resiliencyof a benchmark when tested with the different fault maps can be up to 24%.

Hardware Versus Software Fault Injection of Modern Undervolted SRAMs