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In this project, we investigate the fluctuations in performance caused bychanging the Instruction (I-cache) size and the Data (D-cache) size in the L1cache. We employ the Gem5 framework to simulate a system with varyingspecifications on a single host machine. We utilize the FreqMine benchmarkavailable under the PARSEC suite as the workload program to benchmark oursimulated system. The Out-order CPU (O3) with Ruby memory model was simulatedin a Full-System X86 environment with Linux OS. The chosen metrics deal withHit Rate, Misses, Memory Latency, Instruction Rate, and Bus Traffic within thesystem. Performance observed by varying L1 size within a certain range ofvalues was used to compute Confidence Interval based statistics for relevantmetrics. Our expectations, corresponding experimental observations, anddiscrepancies are also discussed in this report.

System Performance with varying L1 Instruction and Data Cache Sizes: An Empirical Analysis