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In this work, we introduce bitcell array-based support parameters to improvethe prediction accuracy of SRAM-based binarized neural network (SRAM-BNN). Ourapproach enhances the training weight space of SRAM-BNN while requiring minimaloverheads to a typical design. More flexibility of the weight space leads tohigher prediction accuracy in our design. We adapt row digital-to-analog (DAC)converter, and computing flow in SRAM-BNN for bitcell array-based weightsupports. Using the discussed interventions, our scheme also allows a dynamictrade-off of accuracy against latency to address dynamic latency constraints intypical real-time applications. We specifically discuss results on two trainingcases: (i) learning of support parameters on a pre-trained BNN and (ii)simultaneous learning of supports and weight binarization. In the former case,our approach reduces classification error in MNIST by 35.71% (error ratedecreases from 1.4% to 0.91%). In the latter case, the error is reduced by27.65% (error rate decreases from 1.4% to 1.13%). To reduce the poweroverheads, we propose a dynamic drop out a part of the support parameters. Ourarchitecture can drop out 52% of the bitcell array-based support parameterswithout losing accuracy. We also characterize our design under varying degreesof process variability in the transistors.

Supported-BinaryNet: Bitcell Array-based Weight Supports for Dynamic Accuracy-Latency Trade-offs in SRAM-based Binarized Neural Network