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Single-issue processor cores are very energy efficient but suffer from thevon Neumann bottleneck, in that they must explicitly fetch and issue theloads/storse necessary to feed their ALU/FPU. Each instruction spent on movingdata is a cycle not spent on computation, limiting ALU/FPU utilization to 33%on reductions. We propose "Stream Semantic Registers" to boost utilization andincrease energy efficiency. SSR is a lightweight, non-invasive RISC-V ISAextension which implicitly encodes memory accesses as register reads/writes,eliminating a large number of loads/stores. We implement the proposed extensionin the RTL of an existing multi-core cluster and synthesize the design for amodern 22nm technology. Our extension provides a significant, 2x to 5x,architectural speedup across different kernels at a small 11% increase in corearea. Sequential code runs 3x faster on a single core, and 3x fewer cores areneeded in a cluster to achieve the same performance. The utilization increaseto almost 100% in leads to a 2x energy efficiency improvement in a multi-corecluster. The extension reduces instruction fetches by up to 3.5x andinstruction cache power consumption by up to 5.6x. Compilers can automaticallymap loop nests to SSRs, making the changes transparent to the programmer.

Stream Semantic Registers: A Lightweight RISC-V ISA Extension Achieving Full Compute Utilization in Single-Issue Cores