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FPGAs have become a popular choice for deploying deep learning architectures(DLA). There are many researchers that have explored the deployment and mappingof DLA on FPGA. However, there has been a growing need to do design-timehardware-software co-verification of these deployments. To the best of ourknowledge this is the first work that proposes a 2-Level 3-Way (2L-3W)hardware-software co-verification methodology and provides a step-by-step guidefor the successful mapping, deployment and verification of DLA on FPGA boards.The 2-Level verification is to make sure the implementation in each stage(software and hardware) are following the desired behavior. The 3-Wayco-verification provides a cross-paradigm (software, design and hardware)layer-by-layer parameter check to assure the correct implementation and mappingof the DLA onto FPGA boards. The proposed 2L-3W co-verification methodology hasbeen evaluated over several test cases. In each case, the prediction andlayer-by-layer output of the DLA deployed on PYNQ FPGA board (hardware)alongside with the intermediate design results of the layer-by-layer output ofthe DLA implemented on Vivado HLS and the prediction and layer-by-layer outputof the software level (Caffe deep learning framework) are compared to obtain alayer-by-layer similarity score. The comparison is achieved using a completelyautomated Python script. The comparison provides a layer-by-layer similarityscore that informs us the degree of success of the DLA mapping to the FPGA orhelp identify in design time the layer to be debugged in the case ofunsuccessful mapping. We demonstrated our technique on LeNet DLA and Caffeinspired Cifar-10 DLA and the co-verification results yielded layer-by-layersimilarity scores of 99\% accuracy.

2L-3W: 2-Level 3-Way Hardware-Software Co-Verification for the Mapping of Deep Learning Architecture (DLA) onto FPGA Boards