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The tremendous progress in Metal Oxide Semiconductor (MOS) technology hasbeen a direct consequence of device scaling for past several decades. But as wehave entered the nanometer era many problems related to leakage currents andother issues related to variability impacting the yield are of concern. Hereinwe have investigated how the change in the Fin Architecture and Gate Length ofthe MOS device impacts the Threshold Voltage.

Threshold Voltage variation with respect to Gate geometry in Nano-scale MOSFETS