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General trends in computer architecture are shifting more towardsparallelism. Multicore architectures have proven to be a major step inprocessor evolution. With the advancement in multicore architecture,researchers are focusing on finding different solutions to fully utilize thepower of multiple cores. With an ever-increasing number of cores on a chip, therole of cache memory has become pivotal. An ideal memory configuration shouldbe both large and fast, however, in fact, system architects have to strike abalance between the size and access time of the memory hierarchy. It isimportant to know the impact of a particular cache configuration on thethroughput and energy consumption of the system at design time. This paperpresents an enhanced version of previously proposed cache energy and throughputmodels for multicore systems. These models use significantly a smaller numberof input parameters as compared to other models. This paper also validates theproposed models through cycle accurate simulator and a renowned processor powerestimator. The results show that the proposed energy models provide accuracywithin a maximum error range of 10% for single-core processors and around 5%for MPSoCs, and the throughput models result in a maximum error of up to 11.5%for both single and multicore architectures.

Analytical models of Energy and Throughput for Caches in MPSoCs