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In this paper, we propose a Junctionless (JL)/Accumulation Mode (AM)transistor with an access transistor (JL in series with JL/AM transistor) basedcapacitorless Dynamic Random Access Memory (1TDRAM) cell. The JL transistorovercomes the problem of ultrasharp p-n junction associated with conventionalMetal-Oxide-Semiconductor (MOS) in nanoscale regime. The access transistor (AT)is utilized to reduces the leakage, and thus, improves the Retention Time (RT)and Sense Margin (SM) of the proposed capacitorless DRAM cell. Thus, theproposed DRAM cell achieved a maximum SM of ~4.6 {\mu}A/{\mu}m with RT of ~6.5s for a gate length (Lg) of 100nm. Further, this topology shows better gatelength scalability with a fixed gate length of AT and achieves RT of ~100 msand ~10 ms for a scaled gate length of 10 nm at 27 {\deg}C and 85 {\deg}C,respectively.

Improvement in Retention Time of Capacitorless DRAM with Access Transistor