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The new generation of machine learning processors have evolved frommulti-core and parallel architectures that were designed to efficientlyimplement matrix-vector-multiplications (MVMs). This is because at thefundamental level, neural network and machine learning operations extensivelyuse MVM operations and hardware compilers exploit the inherent parallelism inMVM operations to achieve hardware acceleration on GPUs and FPGAs. However,many IoT and edge computing platforms require embedded ML devices close to thenetwork in order to compensate for communication cost and latency. Hence anatural question to ask is whether MVM operations are even necessary toimplement ML algorithms and whether simpler hardware primitives can be used toimplement an ultra-energy-efficient ML processor/architecture. In this paper wepropose an alternate hardware-software codesign of ML and neural networkarchitectures where instead of using MVM operations and non-linear activationfunctions, the architecture only uses simple addition and thresholdingoperations to implement inference and learning. At the core of the proposedapproach is margin-propagation (MP) based computation that maps multiplicationsinto additions and additions into a dynamic rectifying-linear-unit (ReLU)operations. This mapping results in significant improvement in computationaland hence energy cost. In this paper, we show how the MP network formulationcan be applied for designing linear classifiers, shallow multi-layerperceptrons and support vector networks suitable fot IoT platforms and tiny MLapplications. We show that these MP based classifiers give comparable resultsto that of their traditional counterparts for benchmark UCI datasets, with theadded advantage of reduction in computational complexity enabling animprovement in energy efficiency.

Multiplierless and Sparse Machine Learning based on Margin Propagation Networks