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Emerging resistive random-access memory (ReRAM) has recently been intensivelyinvestigated to accelerate the processing of deep neural networks (DNNs). Dueto the in-situ computation capability, analog ReRAM crossbars yield significantthroughput improvement and energy reduction compared to traditional digitalmethods. However, the power hungry analog-to-digital converters (ADCs) preventthe practical deployment of ReRAM-based DNN accelerators on end devices withlimited chip area and power budget. We observe that due to the limitedbit-density of ReRAM cells, DNN weights are bit sliced and correspondinglystored on multiple ReRAM bitlines. The accumulated current on bitlines resultedby weights directly dictates the overhead of ADCs. As such, bitwise weightsparsity rather than the sparsity of the full weight, is desirable forefficient ReRAM deployment. In this work, we propose bit-slice L1, the firstalgorithm to induce bit-slice sparsity during the training of dynamicfixed-point DNNs. Experiment results show that our approach achieves 2xsparsity improvement compared to previous algorithms. The resulting sparsityallows the ADC resolution to be reduced to 1-bit of the most significantbit-slice and down to 3-bit for the others bits, which significantly speeds upprocessing and reduces power and area overhead.

Exploring Bit-Slice Sparsity in Deep Neural Networks for Efficient ReRAM-Based Deployment