English (United Kingdom)

https://curated-unify.zendy.io/wp-json/zendy-region/v1/featured_content/oa?rat=en

https://curated-unify.zendy.io/wp-json/zendy-region/v1/highlighted_journal/

Global: Zendy Plus annual

Presents the access of premium content as premium feature

Premium Content

Presents the keyphrase highlighting as premium feature

Keyphrase Highlighting

Presents the summarisation as premium feature

Summarisation

Insights

Presents the pdf analysis as premium feature

PDF Analysis

Presents the zaia usage as premium feature

ZAIA

Global: Zendy Plus monthly

Global: Zendy Tools annual

Global: Zendy Tools monthly

Global: Zendy Free Plan

Spiking neural networks (SNNs) are the third generation of neural networksand can explore both rate and temporal coding for energy-efficient event-drivencomputation. However, the decision accuracy of existing SNN designs iscontingent upon processing a large number of spikes over a long period.Nevertheless, the switching power of SNN hardware accelerators is proportionalto the number of spikes processed while the length of spike trains limitsthroughput and static power efficiency. This paper presents the first study ondeveloping temporal compression to significantly boost throughput and reduceenergy dissipation of digital hardware SNN accelerators while being applicableto multiple spike codes. The proposed compression architectures consist oflow-cost input spike compression units, novel input-and-output-weighted spikingneurons, and reconfigurable time constant scaling to support large and flexibletime compression ratios. Our compression architectures can be transparentlyapplied to any given pre-designed SNNs employing either rate or temporal codeswhile incurring minimal modification of the neural models, learning algorithms,and hardware design. Using spiking speech and image recognition datasets, wedemonstrate the feasibility of supporting large time compression ratios of upto 16x, delivering up to 15.93x, 13.88x, and 86.21x improvements in throughput,energy dissipation, the tradeoffs between hardware area, runtime, energy, andclassification accuracy, respectively based on different spike codes on aXilinx Zynq-7000 FPGA. These results are achieved while incurring little extrahardware overhead.

Boosting Throughput and Efficiency of Hardware Spiking Neural Accelerators using Time Compression Supporting Multiple Spike Codes