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Heterogeneous 3D System-on-Chips (3D SoCs) are the most promising designparadigm to combine sensing and computing within a single chip. A specialcharacteristic of communication networks in heterogeneous 3D SoCs is thevarying latency and throughput in each layer. As shown in this work, thisvariance drastically degrades the network performance. We contribute aco-design of routing algorithms and router microarchitecture that allows toovercome these performance limitations. We analyze the challenges ofheterogeneity: Technology-aware models are proposed for communication andthereby identify layers in which packets are transmitted slower. Thecommunication models are precise for latency and throughput under zero load.The technology model has an area error and a timing error of less than 7.4% forvarious commercial technologies from 90 to 28nm. Second, we demonstrate how toovercome limitations of heterogeneity by proposing two novel routing algorithmscalled Z+(XY)Z- and ZXYZ that enhance latency by up to 6.5x compared toconventional dimension order routing. Furthermore, we propose a highvertical-throughput router microarchitecture that is adjusted to the routingalgorithms and that fully overcomes the limitations of slower layers. Weachieve an increased throughput of 2 to 4x compared to a conventional router.Thereby, the dynamic power of routers is reduced by up to 41.1% and we achieveimproved flit latency of up to 2.26x at small total router area costs between2.1% and 10.4% for realistic technologies and application scenarios.

NoCs in Heterogeneous 3D SoCs: Co-Design of Routing Strategies and Microarchitectures