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Computationally intensive Inference tasks of Deep neural networks haveenforced revolution of new accelerator architecture to reduce power consumptionas well as latency. The key figure of merit in hardware inference acceleratorsis the number of multiply-and-accumulation operations per watt (MACs/W), where,the state-of-the-arts MACs/W remains several hundreds Giga-MACs/W. We propose aTera-MACS/W neural hardware inference Accelerator (TMA) with 8-bit activationsand scalable integer weights less than 1-byte. The architectures main featureis configurable neural processing element for matrix-vector operations. Theproposed neural processing element has Multiplier-less Massive ParallelProcessor to work without any multiplications, which makes it attractive forenergy efficient high-performance neural network applications. We benchmark oursystems latency, power, and performance using Alexnet trained on ImageNet.Finally, we compared our accelerators throughput and power consumption to theprior works. The proposed accelerator outperforms the state of the art in termsof energy and area achieving 2.3 TMACS/W@1.0 V, 65 nm CMOS technology.

TMA: Tera-MACs/W Neural Hardware Inference Accelerator with a Multiplier-less Massive Parallel Processor