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As designs for superconducting qubits become more complex, 3D integration oftwo or more vertically bonded chips will become necessary to enable increaseddensity and connectivity. Precise control of the spacing between these chips isrequired for accurate prediction of circuit performance. In this paper, wedemonstrate an improvement in the planarity of bonded superconducting qubitchips while retaining device performance by utilizing hard-stop silicon spacerposts. These silicon spacers are defined by etching several microns into asilicon substrate and are compatible with 3D-integrated qubit fabrication. Thisincludes fabrication of Josephson junctions, superconducting air-bridgecrossovers, underbump metallization and indium bumps. To qualify the integratedprocess, we demonstrate high-quality factor resonators on the etched surfaceand measure qubit coherence (T1, T2,echo > 40 {\mu}s) in the presence ofsilicon posts as near as 350 {\mu}m to the qubit.

Silicon Hard-Stop Spacers for 3D Integration of Superconducting Qubits