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To mitigate the performance gap between CPU and the main memory, multi-levelcache architectures are widely used in modern processors. Therefore, modelingthe behaviors of the downstream caches becomes a critical part of the processorperformance evaluation in the early stage of Design Space Exploration (DSE). Inthis paper, we propose a fast and accurate L2 cache reuse distance histogrammodel, which can be used to predict the behaviors of the multi-level cachearchitectures where the L1 cache uses the LRU replacement policy and the L2cache uses LRU/Random replacement policies. We use the profiled L1 reusedistance histogram and two newly proposed metrics, namely the RST table and theHit-RDH, that describing more detailed information of the software traces asthe inputs. For a given L1 cache configuration, the profiling results can bereused for different configurations of the L2 cache. The output of our model isthe L2 cache reuse distance histogram, based on which the L2 cache miss ratescan be evaluated. We compare the L2 cache miss rates with the results from gem5cycle-accurate simulations of 15 benchmarks chosen from SPEC CPU 2006 and 9benchmarks from SPEC CPU 2017. The average absolute error is less than 5%,while the evaluation time for each L2 configuration can be sped up almost 30Xfor four L2 cache candidates.

Fast Modeling L2 Cache Reuse Distance Histograms Using Combined Locality Information from Software Traces