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This paper investigates bandwidth-efficient DRAM caching for hybrid DRAM +3D-XPoint memories. 3D-XPoint is becoming a viable alternative to DRAM as itenables high-capacity and non-volatile main memory systems; however, 3D-XPointhas 4-8x slower read, and worse writes. As such, effective DRAM caching infront of 3D-XPoint is important to enable a high-capacity, low-latency, andhigh-write-bandwidth memory. There are two major approaches for DRAM cachedesign: (1) a Tag-Inside-Cacheline (TIC) organization that optimizes for hits,by storing tag next to each line such that one access gets both tag and data,and (2) a Tag-Outside-Cacheline (TOC) organization that optimizes for misses,by storing tags from multiple data-lines together such that one tag-access getsinfo for several data-lines. Ideally, we desire the low hit-latency of TIC, andthe low miss-bandwidth of TOC. To this end, we propose TicToc, an organizationthat provisions both TIC and TOC to get hit and miss benefits of both.  However, we find that naively combining both actually performs worse thanTIC, because one needs to pay bandwidth to maintain both metadata. The maincontribution of this work is developing architectural techniques to reduce thebandwidth of maintaining both TIC and TOC metadata. We find the majority of thebandwidth cost is due to maintaining TOC dirty bits. We propose DRAM CacheDirtiness Bit, which carries DRAM cache dirty info to last-level caches, toprune repeated dirty-bit checks for known dirty lines. We then proposePreemptive Dirty Marking, which predicts which lines will be written andproactively marks dirty bit at install time, to amortize the initial dirty-bitupdate. Our evaluations on a 4GB DRAM cache with 3D-XPoint memory show thatTicToc enables 10% speedup over baseline TIC, nearing 14% speedup possible withan idealized DRAM cache w/ 64MB of SRAM tags, while needing only 34KB SRAM.

TicToc: Enabling Bandwidth-Efficient DRAM Caching for both Hits and Misses in Hybrid Memory Systems