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Machine learning algorithms have made significant advances in manyapplications. However, their hardware implementation on the state-of-the-artplatforms still faces several challenges and are limited by various factors,such as memory volume, memory bandwidth and interconnection overhead. Theadoption of the crossbar architecture with emerging memory technology partiallysolves the problem but induces process variation and other concerns. In thispaper, we will present novel solutions to two fundamental issues in crossbarimplementation of Artificial Intelligence (AI) algorithms: device variation andinsufficient interconnections. These solutions are inspired by the statisticalproperties of algorithms themselves, especially the redundancy in neuralnetwork nodes and connections. By Random Sparse Adaptation and pruning theconnections following the Small-World model, we demonstrate robust andefficient performance on representative datasets such as MNIST and CIFAR-10.Moreover, we present Continuous Growth and Pruning algorithm for futurelearning and adaptation on hardware.

Towards Efficient Neural Networks On-a-chip: Joint Hardware-Algorithm Approaches