English (United Kingdom)

https://curated-unify.zendy.io/wp-json/zendy-region/v1/featured_content/oa?rat=en

https://curated-unify.zendy.io/wp-json/zendy-region/v1/highlighted_journal/

Global: Zendy Plus annual

Presents the access of premium content as premium feature

Premium Content

Presents the keyphrase highlighting as premium feature

Keyphrase Highlighting

Presents the summarisation as premium feature

Summarisation

Insights

Presents the pdf analysis as premium feature

PDF Analysis

Presents the zaia usage as premium feature

ZAIA

Global: Zendy Plus monthly

Global: Zendy Tools annual

Global: Zendy Tools monthly

Global: Zendy Free Plan

The paper presents simulation study of thin ferroelectrics (Si doped HfO2,PZT) PGP FDSOI NCFETs at circuit level for high performance, low VDD low-powerdigital circuits. The baseline PGP FDSOI MOSFET has 20 nm metal gate lengthwith supply voltage varying from 0.5 V to 0.9 V. The circuits studied were3-stage CMOS ring oscillator, NAND-2 and NOR-2 gates at a frequency of 20 GHz.The paper shows that HfO2 FDSOI NCFET based NAND-2 gates can providesignificant reduction in average power consumption, which was ~66% that ofbaseline FDSOI MOSFET based NAND-2 gates for comparable performance. For thesame performance, the average power consumption for PZT FDSOI NCFET basedNAND-2 gate was ~86% that of baseline FDSOI MOSFET based NAND-2 gate. Thepower-delay product of HfO2 FDSOI NCFET based gates was found to be ~24% lowerthan baseline FDSOI MOSFET based gates and that of PZT FDSOI NCFET based gateswas found to be ~21% less than that of baseline FDSOI MOSFET based gates. Theperformance of HfO2 FDSOI NCFET based gates with increased fan-in and fan-outwas also found to be superior to PZT FDSOI NCFET based gates and baseline FDSOIMOSFET based gates.

Performance Considerations of Thin Ferroelectrics (~10 nm HfO2, ~20 nm PZT) FDSOI NCFETs for Digital Circuits at Reduced Power Consumption