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Monolithic 3D (M3D) technology enables high density integration, performance,and energy-efficiency by sequentially stacking tiers on top of each other.M3D-based network-on-chip (NoC) architectures can exploit these benefits byadopting tier partitioning for intra-router stages. However, conventionalfabrication methods are infeasible for M3D-enabled designs due to temperaturerelated issues. This has necessitated lower temperature andtemperature-resilient techniques for M3D fabrication, leading to inferiorperformance of transistors in the top tier and interconnects in the bottomtier. The resulting inter-tier process variation leads to performancedegradation of M3D-enabled NoCs. In this work, we demonstrate that withoutconsidering inter-tier process variation, an M3D-enabled NoC architectureoverestimates the energy-delay-product (EDP) on average by 50.8% for a set ofSPLASH-2 and PARSEC benchmarks. As a countermeasure, we adopt a processvariation aware design approach. The proposed design and optimization methoddistribute the intra-router stages and inter-router links among the tiers tomitigate the adverse effects of process variation. Experimental results showthat the NoC architecture under consideration improves the EDP by 27.4% onaverage across all benchmarks compared to the process-oblivious design.

Inter-Tier Process Variation-Aware Monolithic 3D NoC Architectures