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Electronic circuit behavioral models built with hardware description/modelinglanguages such as Verilog-AMS for system-level simulations are typicallyfunctional models. They do not capture the physical design (layout) informationof the target design. Numerous iterations of post-layout design adjustments areusually required to ensure that design specifications are met with the presenceof layout parasitics. In this paper a paradigm shift of the current trend ispresented that integrates layout-level information in Verilog-AMS throughmetamodels such that system-level simulation of a mixed-signal circuit/systemis realistic and as accurate as true parasitic netlist simulation. Thesimulations performed with these parasitic-aware models can be used to estimatesystem performance without layout iterations. We call this new form ofVerilog-AMS as iVAMS (i.e. Intelligent Verilog-AMS). We call this iVAMS 1.0 asit is simple polynomial-metamodel integrated Intelligent Verilog-AMS. As aspecific case study, a voltage-controlled oscillator (VCO) Verilog-AMSbehavioral model and design flow are proposed to assist fast PLL design spaceexploration. The PLL simulation employing quadratic metamodels achievesapproximately 10X speedup compared to that employing the layout extracted,parasitic netlist. The simulations using this behavioral model attain highaccuracy. The observed error for the simulated lock time and average powerdissipation are 0.7% and 3%, respectively. This behavioral metamodel approachbridges the gap between layout-accurate but fast simulation and design spaceexploration. The proposed method also allows much shorter design verificationand optimization to meet stringent time-to-market requirements. Compared to theoptimization using the layout netlist, the runtime using the behavioral modelis reduced by 88.9%.

iVAMS 1.0: Polynomial-Metamodel-Integrated Intelligent Verilog-AMS for Fast, Accurate Mixed-Signal Design Optimization