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This work presents a novel general compact model for 7nm technology nodedevices like FinFETs. As an extension of previous conventional compact modelthat based on some less accurate elements including one-dimensional Poissonequation for three-dimensional devices and analytical equations for shortchannel effects, quantum effects and other physical effects, the generalcompact model combining few TCAD calibrated compact models with statisticalmethods can eliminate the tedious physical derivations. The general compactmodel has the advantages of efficient extraction, high accuracy, strong scalingcapability and excellent transfer capability. As a demo application, two keydesign knobs of FinFET and their multiple impacts on RC control ESD power clampcircuit are systematically evaluated with implementation of the newly proposedgeneral compact model, accounting for device design, circuit performanceoptimization and variation control. The performance of ESD power clamp can beimproved extremely. This framework is also suitable for pathfinding researcheson 5nm node gate-all-around devices, like nanowire (NW) FETs, nanosheet (NSH)FETs and beyond.

A Novel General Compact Model Approach for 7nm Technology Node Circuit Optimization from Device Perspective and Beyond