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The emerging mobile devices in this era of internet-of-things (IoT) require adedicated processor to enable computationally intensive applications such asneuromorphic computing and signal processing. Vector-by-matrix multiplication(VMM) is the most prominent operation in these applications. Therefore, thereis a critical need for compact and ultralow-power VMM blocks to performresource-intensive low-to-moderate precision computations. To this end, in thiswork, for the first time, we propose a time-domain mixed-signal VMM exploitinga modified configuration of 1MOSFET-1RRAM (1T-1R) array. The proposed VMMovercomes the energy inefficiency of the current-mode VMM approaches based onRRAMs. A rigorous analysis of the different non-ideal factors affecting thecomputational precision indicates that the non-negligible minimum cellcurrents, channel length modulation (CLM) and drain-induced barrier lowering(DIBL) are the dominant mechanisms degrading the precision of the proposed VMM.Our results also indicate that there exists a trade-off between thecomputational precision, dynamic range, and the area- and energy-efficiency ofthe proposed VMM approach. Therefore, we provide the necessary designguidelines for optimizing the performance. Our preliminary results show that aneffective computational precision of 6-bits is achievable owing to an inherentcompensation effect in the modified 1T-1R blocks. Furthermore, a 4-bit 200x200VMM utilizing the proposed approach exhibits a significantly high energyefficiency of ~1.5 POps/J and a throughput of 2.5 TOps/s including thecontribution from the input/output (I/O) circuitry.

Energy-Efficient Moderate Precision Time-Domain Mixed-signal Vector-by-Matrix Multiplier Exploiting 1T-1R Arrays