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Deep packet inspection via regular expression (RE) matching is a crucial taskof network intrusion detection systems (IDSes), which secure Internetconnection against attacks and suspicious network traffic. Monitoringhigh-speed computer networks (100 Gbps and faster) in a single-box solutiondemands that the RE matching, traditionally based on finite automata (FAs), isaccelerated in hardware. In this paper, we describe a novel FPGA architecturefor RE matching that is able to process network traffic beyond 100 Gbps. Thekey idea is to reduce the required FPGA resources by leveraging approximatenondeterministic FAs (NFAs). The NFAs are compiled into a multi-stagearchitecture starting with the least precise stage with a high throughput andending with the most precise stage with a low throughput. To obtain the reducedNFAs, we propose new approximate reduction techniques that take into accountthe profile of the network traffic. Our experiments showed that using ourapproach, we were able to perform matching of large sets of REs from SNORT, apopular IDS, on unprecedented network speeds.

Deep Packet Inspection in FPGAs via Approximate Nondeterministic Automata