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Resistive random access memories (RRAM) are novel nonvolatile memorytechnologies, which can be embedded at the core of CMOS, and which could beideal for the in-memory implementation of deep neural networks. A particularlyexciting vision is using them for implementing Binarized Neural Networks(BNNs), a class of deep neural networks with a highly reduced memory footprint.The challenge of resistive memory, however, is that they are prone to devicevariation, which can lead to bit errors. In this work we show that BNNs cantolerate these bit errors to an outstanding level, through simulations ofnetworks on the MNIST and CIFAR10 tasks. If a standard BNN is used, up to 10^-4bit error rate can be tolerated with little impact on recognition performanceon both MNIST and CIFAR10. We then show that by adapting the training procedureto the fact that the BNN will be operated on error-prone hardware, thistolerance can be extended to a bit error rate of 4x10^-2. The requirements forRRAM are therefore a lot less stringent for BNNs than more traditionalapplications. We show, based on experimental measurements on a RRAM HfO2technology, that this result can allow reduce RRAM programming energy by afactor 30.

Outstanding Bit Error Tolerance of Resistive RAM-Based Binarized Neural Networks