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In 2019, the rapid rate at which GPU manufacturers refresh their designs,coupled with their reluctance to disclose microarchitectural details, is stilla hurdle for those software designers who want to extract the highest possibleperformance. Last year, these very reasons motivated us to dissect the VoltaGPU architecture using microbenchmarks.  The introduction in August 2018 of Turing, NVidia's latest architecture,pressed us to update our study. In this report, we examine Turing and compareit quantitatively against previous NVidia GPU generations. Specifically, westudy the T4 GPU: a low-power board aiming at inference applications. Wedescribe its improvements against its inference-oriented predecessor: the P4GPU based on the Pascal architecture. Both T4 and P4 GPUs achieve significantlyhigher frequency-per-Watt figures than their full-size counterparts.  We study the performance of the T4's TensorCores, finding a much higherthroughput on low-precision operands than on the P4 GPU. We reveal that Turingintroduces new instructions that express matrix math more succinctly. We mapTuring's instruction space, finding the same encoding as Volta, and additionalinstructions. We reveal that the Turing TU104 chip has the same memoryhierarchy depth as the Volta GV100; cache levels sizes on the TU104 arefrequently twice as large as those found on the Pascal GP104. We benchmark eachconstituent of the T4 memory hierarchy and find substantial overall performanceimprovements over its P4 predecessor. We studied how clock throttling affectscompute-intensive workloads that hit power or thermal limits.  Many of our findings are novel, published here for the first time. All ofthem can guide high-performance software developers get closer to the GPU'speak performance.

Dissecting the NVidia Turing T4 GPU via Microbenchmarking