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Byte-addressable non-volatile main memory (NVM) demands transactionalmechanisms to access and manipulate data on NVM atomically. Those transactionmechanisms often employ a logging mechanism (undo logging or redo logging).However, the logging mechanisms can bring large runtime overhead (8%-49% in ourevaluation), and 41%-78% of the overhead attributes to the frequent cache-lineflushing. Such large overhead significantly diminishes the performance benefitsoffered by NVM. In this paper, we introduce a new method to reduce the overheadof cache-line flushing for logging-based transactions. Different from thetraditional method that works at the program level and leverages programsemantics to reduce the logging overhead, we introduce architecture awareness.In particular, we do not flush certain cache blocks, as long as they areestimated to be eliminated out of the cache because of the hardware cachingmechanism (e.g., the cache replacement algorithm). Furthermore, we coalescethose cache blocks with low dirtiness to improve the efficiency of cache-lineflushing. We implement an architecture-aware, high performance transactionruntime system for persistent memory, Archapt. Our results show that comparingwith an undo logging (PMDK) and a redo logging (Mnemosyne), Archapt reducescache-line flushing by 66% and improves system throughput by 19% on average(42% at most). Our crash tests with four hardware caching policies show thatArchapt provides a strong guarantee on crash consistency.

Architecture-Aware, High Performance Transaction for Persistent Memory