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In the area of physical attacks, system-on-chip (SoC) designs have notreceived the same level of attention as simpler micro-controllers. We try tomodel the behavior of secure software running on a superscalar out-of-ordermicroprocessor typical of more complex SoC, in the presence of electromagnetic(EM) pulses. We first show that it is possible, in a black box approach, tocorrupt the loop iteration count of both original and hardened versions of twosensitive loops. We propose a characterization methodology based on very simplecodes, to understand and classify the fault effects at the level of theinstruction set architecture (ISA). The resulting classification includes thewell established instruction skip and register corruption models, as well asnew effects specific to more complex processors, such as operand substitution,multiple correlated register corruptions, advanced control-flow hijacking, andcombinations of all reported effects. This diversity and complexity of effectscan lead to powerful attacks. The proposed methodology and fault classificationat ISA level is a first step towards a more complete characterization. It isalso a tool supporting the designers of software and hardware countermeasures.

Studying EM Pulse Effects on Superscalar Microarchitectures at ISA Level