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Three-dimensional deconvolution is widely used in many computer visionapplications. However, most previous works have only focused on accelerating 2Ddeconvolutional neural networks (DCNNs) on FPGAs, while the acceleration of 3DDCNNs has not been studied in depth as they have higher computationalcomplexity and sparsity than 2D DCNNs. In this paper, we focus on theacceleration of both 2D and 3D DCNNs on FPGAs by proposing efficient schemesfor mapping 2D and 3D DCNNs on a uniform architecture. By implementing ourdesign on the Xilinx VC709 platform for four real-life 2D and 3D DCNNs, we canachieve up to 3.0 TOPS with high hardware efficiency. Comparisons with CPU andGPU solutions demonstrate that we can achieve an improvement of up to 63.3X inthroughput relative to a CPU solution and an improvement of up to 8.3X inenergy efficiency compared to a GPU solution.

Towards a Uniform Architecture for the Efficient Implementation of 2D and 3D Deconvolutional Neural Networks on FPGAs