English (United Kingdom)

https://curated-unify.zendy.io/wp-json/zendy-region/v1/featured_content/oa?rat=en

https://curated-unify.zendy.io/wp-json/zendy-region/v1/highlighted_journal/

Global: Zendy Plus annual

Presents the access of premium content as premium feature

Premium Content

Presents the keyphrase highlighting as premium feature

Keyphrase Highlighting

Presents the summarisation as premium feature

Summarisation

Insights

Presents the pdf analysis as premium feature

PDF Analysis

Presents the zaia usage as premium feature

ZAIA

Global: Zendy Plus monthly

Global: Zendy Tools annual

Global: Zendy Tools monthly

Global: Zendy Free Plan

Convolutional Neural Networks (CNNs) have gained widespread popularity in thefield of computer vision and image processing. Due to huge computationalrequirements of CNNs, dedicated hardware-based implementations are beingexplored to improve their performance. Hardware platforms such as FieldProgrammable Gate Arrays (FPGAs) are widely being used to design parallelarchitectures for this purpose. In this paper, we analyze Winograd minimalfiltering or fast convolution algorithms to reduce the arithmetic complexity ofconvolutional layers of CNNs. We explore a complex design space to find thesets of parameters that result in improved throughput and power-efficiency. Wealso design a pipelined and parallel Winograd convolution engine that improvesthe throughput and power-efficiency while reducing the computational complexityof the overall system. Our proposed designs show up to 4.75$\times$ and1.44$\times$ improvements in throughput and power-efficiency, respectively, incomparison to the state-of-the-art design while using approximately2.67$\times$ more multipliers. Furthermore, we obtain savings of up to 53.6\%in logic resources compared with the state-of-the-art implementation.

Towards Design Space Exploration and Optimization of Fast Algorithms for Convolutional Neural Networks (CNNs) on FPGAs