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The ubiquity of accelerators in high-performance computing has drivenprogramming complexity beyond the skill-set of the average domain scientist. Tomaintain performance portability in the future, it is imperative to decouplearchitecture-specific programming paradigms from the underlying scientificcomputations. We present the Stateful DataFlow multiGraph (SDFG), adata-centric intermediate representation that enables separating programdefinition from its optimization. By combining fine-grained data dependencieswith high-level control-flow, SDFGs are both expressive and amenable to programtransformations, such as tiling and double-buffering. These transformations areapplied to the SDFG in an interactive process, using extensible patternmatching, graph rewriting, and a graphical user interface. We demonstrate SDFGson CPUs, GPUs, and FPGAs over various motifs --- from fundamental computationalkernels to graph analytics. We show that SDFGs deliver competitive performance,allowing domain scientists to develop applications naturally and port them toapproach peak hardware performance without modifying the original scientificcode.

Stateful Dataflow Multigraphs: A Data-Centric Model for Performance Portability on Heterogeneous Architectures