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The current state of the art of Simultaneous Localisation and Mapping, orSLAM, on low power embedded systems is about sparse localisation and mappingwith low resolution results in the name of efficiency. Meanwhile, research inthis field has provided many advances for information rich processing andsemantic understanding, combined with high computational requirements forreal-time processing. This work provides a solution to bridging this gap, inthe form of a scalable SLAM-specific architecture for depth estimation fordirect semi-dense SLAM. Targeting an off-the-shelf FPGA-SoC this acceleratorarchitecture achieves a rate of more than 60 mapped frames/sec at a resolutionof 640x480 achieving performance on par to a highly-optimised parallelimplementation on a high-end desktop CPU with an order of magnitude improvedpower consumption. Furthermore, the developed architecture is combined with ourprevious work for the task of tracking, to form the first complete acceleratorfor semi-dense SLAM on FPGAs, establishing the state of the art in the area ofembedded low-power systems.

A Scalable FPGA-based Architecture for Depth Estimation in SLAM