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DRAM-based main memory and its associated components increasingly account fora significant portion of application performance bottlenecks and power budgetdemands inside the computing ecosystem. To alleviate the problems of storagedensity and power constraints associated with DRAM, system architects areinvestigating alternative non-volatile memory technologies such as Phase ChangeMemory (PCM) to either replace or be used alongside DRAM memory. While suchalternative memory types offer many promises to overcome the DRAM-relatedissues, they present a significant security threat to the users due topersistence of memory data even after power down.  In this paper, we investigate smart mechanisms to obscure the data left innon-volatile memory after power down. In particular, we analyze the effect ofusing a single encryption algorithm versus differentiated encryption based onthe security needs of the application phases. We also explore the effect ofencryption on a hybrid main memory that has a DRAM buffer cache plus PCM mainmemory. Our mechanism takes into account the limited write endurance problemassociated with several non-volatile memory technologies including PCM, andavoids any additional writes beyond those originally issued by theapplications. We evaluate using Gem5 simulator and SPEC 2006 applications, andshow the performance and power overheads of our proposed design.

Architecting Non-Volatile Main Memory to Guard Against Persistence-based Attacks