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Deep Neural Networks (DNNs) have been established as the state-of-the-artalgorithm for advanced machine learning applications. Recently, CapsuleNetshave improved the generalization ability, as compared to DNNs, due to theirmulti-dimensional capsules. However, they pose high computational and memoryrequirements, which makes energy-efficient inference a challenging task. Inthis paper, we perform an extensive analysis to demonstrate their keylimitations due to intense memory accesses and large on-chip memoryrequirements. To enable efficient CaspuleNet inference accelerators, we proposea specialized on-chip memory hierarchy which minimizes the off-chip memoryaccesses, while efficiently feeding the data to the accelerator. We analyze theon-chip memory requirements for each memory component of the architecture. Byleveraging this analysis, we propose a methodology to explore different on-chipmemory designs and a power-gating technique to further reduce the energyconsumption, depending upon the utilization across different operations of aCapsuleNet. Our memory designs can significantly reduce the energy consumptionof the on-chip memory by up to 86%, when compared to a state-of-the-art memorydesign. Since the power consumption of the memory elements is the majorcontributor in the power breakdown of the CapsuleNet accelerator, as we willalso show in our analyses, the proposed memory design can effectively reducethe overall energy consumption of the complete CapsuleNet acceleratorarchitecture.

CapStore: Energy-Efficient Design and Management of the On-Chip Memory for CapsuleNet Inference Accelerators