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Memory accounts for a considerable portion of the total power budget and areaof digital systems. Furthermore, it is typically the performance bottleneck ofthe processing units. Therefore, it is critical to optimize the memory withrespect to the product of power, area, and delay (PAD). We propose a hybridcell assignment method based on multi-sized and dual-Vth SRAM cells whichimproves the PAD cost function by 34% compared to the conventional cellassignment. We also utilize the sizing of SRAM cells for minimizing the DataRetention Voltage (DRV), and voltages for the read and write operations in theSRAM array. Experimental results in a 32nm technology show that combining theproposed hybrid cell assignment and the cell sizing methods can lower PAD by upto 41% when compared to the conventional cell design and assignment.

Hybrid Cell Assignment and Sizing for Power, Area, Delay Product Optimization of SRAM Arrays